1. Field of the Invention
The present invention relates to a static memory cell more particularly, the present invention relates to a solid-state bi-stable circuit functioning as a six-bulk transistor static memory cell having each gate of the six transistors positioned in parallel with each other.
2. Description of Related Art
In today's semiconductor industry, solid-state memory cells are usually fabricated by using metal-oxide-semiconductor field effect transistors ("MOSFETs"). Generally stated, static memory cells are formed by interconnecting two inverters together so that the input of a first inverter is tied to the output of a second inverter and vice versa. Such interconnections create positive feedback which allows the memory cell to store data, either an active "high" or "low" input (i.e., a logic "1" or "0"). Data is stored in these memory cells during a "write cycle" and that data is subsequently read during a "read" cycle. Static memory is typically used in computers such as desk and lap top personal computers, as well as many other industrial applications. As computer technology strives toward smaller and more powerful computer systems, the need for smaller and more stable memory devices increases.
A standard static memory cell commonly used in the industry is a six-bulk transistor static memory cell. An example of the conventional six-bulk transistor static memory cell (hereinafter referred to as a "6T cell") is shown in FIG. 1. The 6T cell 1 comprises four latch transistors 2-5 and two access transistors 6-7, each of which having a drain, source and gate. The latch transistors 2-5 include a pair of n-channel pull-down transistors 2 and 3 and a pair of p-channel load transistors 4 and 5, all of which are interconnected so as to form two CMOS inverters coupled in a positive feedback orientation so as to form a memory cell as briefly described above. The pair of n-channel access transistors 6 and 7 are coupled to the 6T cell 1 to allow communication between the cell 1 and an external device through a pair of bitlines 12 and 13. The manner in which the above-indicated transistors are interconnected is set forth below.
With respect to the interconnection of the latch transistors 2-5, a drain of a first pull-down transistor 2d is coupled to a drain of a first load transistor 4d at a first storage node 8 and a drain of a second pull-down transistor 3d is coupled to a drain of a second load transistor 5d at a storage source node 9. These nodes 8 and 9 store opposite voltages; namely a logic "1" or "0". Sources of the first and second load transistors 4s and 5s are coupled to a common power line (hereinafter referred to as a "Vcc line") 10 while sources of the first and second pull-down transistors 2s and 3s are coupled to a common ground line 11 (hereinafter referred to as a "Vss line"). Gates of the first pull-down and load transistors 2g and 4g are coupled together and connected to the second storage node 9 and gates of the second pull-down and load transistors 3g and 5g are coupled together and connected to the first storage node 8.
With respect to the access transistors 6 and 7, each source of the first and second access transistors 6s and 7s is coupled to the first and second storage nodes 8 and 9, respectively. A drain 6d of a first access transistor 6 is coupled to a bitline 12, referred to as BL, which operates as a data line to read data from and write data into the memory cell 1. A drain 7d of a second access transistor 7 is similarly coupled to another bitline 13 called BL. In addition, both gates 6g and 7g are coupled to a wordline 14 which, in this invention, is laid out perpendicular to the gates of the load and pull-down transistors 2g-5g but parallel to the Vcc and Vss lines 10 and 11.
The 6T cell 1 is accessed by applying a positive voltage to the wordline 14 so that both of the access transistors 6 and 7 are turned on. This allows one of the two bitlines 12 and 13 to sense the contents of the 6T cell 1 based on the voltage at either the first or second storage nodes 8 and 9.
For example, if storage node 8 is at a high (Vcc) voltage and storage node 9 is at the ground potential (Vss), when the wordline 14 is brought to a high voltage, the pull-down transistor 3 and the second access transistor 7 are both tuned on and will thus pull the bitline BL 13 down toward the ground potential Vss. Moreover, the first load transistor 4 and the first access transistor 6 are also tuned on; thus the bitline BL 12 will be pulled up towards the Vcc potential. Thus the state of the cell 1 ("1" or "0") can be determined by sensing the difference in potential between the bitlines 12 and 13.
Conversely, writing a "1" or a "0" into the cell 1 can be accomplished by forcing the bitline 12 or the bitline 13 to either Vcc or Vss and then raising the wordline 14. The potential placed on either the bitline 12 or the bitline 13 will then be transferred to the storage node 8 or 9, respectively, forcing the cell 1 into either a corresponding "1" state or a "0" state.
The conventional 6T cell 1 offers certain advantages associated with being a CMOS circuit comprising both n-channel and p-channel transistors; namely, the circuit does not experience any current flow from the Vcc line 10 to the Vss line 11 when the 6T cell 1 is simply maintaining stored information due to the use of p-channel devices for the load transistors 4 and 5, as illustrated in FIG. 1. For example, the first n-channel and the first p-channel transistors 2 and 4 are in series between the Vcc and Vss lines 10 and 11. Since these transistors are complementary, e.g. they are activated by opposite polarity signals placed on their respective gates 2g and 4g, the first n-channel pull-down transistor 2 is turned on, the first p-channel load transistor 4 is turned off. The same condition exists for the second pull-down and load transistors 3 and 5. As a result, the memory cell 1 does not experience large power consumption.
Another advantage of the 6T cell is the fact that the p-channel loads are "active" loads; that is, their current-carrying capability varies with the voltage on their gates. This means that, for example, if storage node 8 is high, the gate of the p-channel load transistor 4 is held low by the opposite storage node. Thus, since the voltage between the gate and source (which is tied to the Vcc line) of this transistor 4 is negative, it is turned on into a low-impedance state. Therefore, if the high voltage on storage node 8 is perturbed by random noise, for example, so that it is brought to a potential between Vss and Vcc, the p-channel load transistor 4 can supply enough current to bring the storage node 8 back up to the Vcc potential quickly.
This is especially important for smaller memory cells, which do not have much parasitic capacitance tied to their storage nodes and are therefore more susceptible to data loss due to uncontrollable perturbations. However, the conventional 6T cell 1 is reasonably large in size and thus, is not cost effective in today's competitive semiconductor market.
Commonly, in order to decrease the size of the static memory cells for cost saving reasons, the load transistors 4 and 5 in the 6T cell are substituted with resistors 15 and 16 to produce a 4T-2R cell layout shown in FIG. 2. Since such resistors are capable of being physically folded over the pull-down transistors 2 and 3 by using another layer of material, area usage is maximized. However, in view of the fact that the 4T-2R cell includes resistors 15 and 16 in lieu of load transistors 4 and 5 as shown in FIG. 1, the cell sacrifices the above-mentioned advantages associated with 6T CMOS circuitry.
More specifically, as previously mentioned, when the 6T cell is maintaining stored information, it does not experience any current flow between its Vcc to Vss lines because one transistor (either a load or pull-down transistor) is always off. On the other hand, in the 4T-2R cell, when it is storing information, one of the pull-down transistors is conducting which causes current to flow between the Vcc and Vss lines which implies a high power consumption. In older technology, such current was easily controlled by implementing resistors having a large resistance. The larger memory cells of these older technologies had large parasitic capacitances tied to their storage nodes, so that outside perturbations on a charge stored on the storage nodes (due to impacts by alpha particles, for example) have a small effect on the voltage of the storage node. Thus, a high-current load device was not needed to pull up a perturbed high storage node.
However, as cell sizes have decreased, cell capacitances have also decreased and a load device with higher current capacity is needed for cell stability. Such a device can be obtained by lowering the resistance of a load resistor, but this would increase the power consumption of the cell, eventually to unacceptable levels. The 6T cell design uses active loads to "decouple" power consumption and all stability requirements.
In the marketplace, there has been a demand for a static memory cell that provides stability and low power consumption of the 6T cell with the area saving qualities of the 4T-2R cell. As a result, an alternate cell layout had been developed; namely, a circuit substituting polysilicon thin-film transistors 17 and 18 in lieu of the load transistors 4 and 5. The thin-film transistors 17 and 18 are capable of being folded over the lower, bulk silicon transistors 2 and 3 to reduce area usage. Moreover, the circuit has overcomes large power dissipation and cell instability associated with the 4T-2R cell by using transistors in lieu of resistors. However, the disadvantages associated with such fabrication is that the cell requires at least three levels of polysilicon and thus, it quite complex and costly to manufacture.
Hence, it would be desirable to fabricate a 6T cell having a smaller area than conventional 6T cells while providing cell stability and negligible power dissipation.
Based on the foregoing, it can be appreciated that there is a need to provide a stable memory cell which maximizes area usage. Therefore, it is an object of the present invention to provide solid-state bi-stable circuit functioning as a six-bulk transistor static memory cell having each gate of the six transistors positioned in parallel with each other.
Another object of the present invention is to provide a memory cell having a smaller area usage without sacrificing cell stability.
A further object of the present invention is to provide a memory cell having its Vcc and Vss lines to be perpendicular with a plurality of wordlines.
Yet another object of the present invention is to provide a memory cell having its transistors fabricated with a single polysilicon layer.
Another object of the present invention is to provide a memory cell having a substantially square shape for easy packaging.